The present invention relates to a semiconductor memory device; and, more particularly, to a data transfer path for use in the semiconductor memory device.
As well-known in the art, a semiconductor memory device is a semiconductor device for storing a lot of data and providing desired data out of the stored data. In the main operation of the semiconductor memory device, there are a write operation for storing data and a read operation for outputting selected data from the stored data. Further, there is a precharge operation for getting read and write operations ready when those operations are not done. In addition, the semiconductor memory device which employs a capacitor in the unit of data storage like DRAM also performs a refresh operation for compensating for a natural leakage of a signal stored in the capacitor.
The semiconductor memory device is made in a manner that unit cells as a basic component for data storage are arranged in a matrix form to efficiently store numerous data. Each of the unit cells arranged in the matrix form is disposed at a point where a plurality of word lines crossing in a horizontal direction intersects a plurality of bit lines crossing in a longitudinal direction. Each of the word lines corresponds to a row address, while each of the bit lines corresponds to a column address. In general, in case of performing the read or write operation, a row address is first inputted and a corresponding one is selected from the plurality of word lines. Then, a column address is inputted and a corresponding one is selected from the plurality of bit lines. The data of unit cell designated by the selected word line and bit line indicates data to be accessed.
For efficient structure, the semiconductor device receives both a row address and a column address through one address input pad, and shares a pad where data is inputted/outputted. During the read operation, data is outputted through an input/output pad, and during the write operation, data is inputted through the input/output pad. And one data transfer path is established between the unit cell and the input/output pad. In the data transfer path, a transfer circuit for the write operation and a transfer circuit for the read operation are provided for transferring data in predetermined directions during those two operations. Each transfer circuit includes a sense amplifier for sensing and amplifying a data transfer line and a data signal transferred to the data transfer line.
In the semiconductor memory device, the unit cell is manufactured to store and maintain a minimum data signal for more data storage. Therefore, when there is a need to output a data signal stored in the unit cell, it is first required to sense and amplify the data signal in the unit cell.
There exists a large difference between a magnitude of a data signal outputted through the data input/output pad and that of a data signal stored in the unit cell. Further, a parasitic resistance of the data transfer line connected between the unit cell and the input/output pad is very large compared with the data signal stored in the unit cell. Accordingly, the semiconductor memory device amplifies a data signal stored in the unit cell in stages and then outputs it to the data pad to effectively access the data during the read operation.
In order to amplify the data signal in stages, the conventional semiconductor memory device is provided with two sense amplifiers, wherein a data transfer line is coupled between these two sense amplifiers. The first sense amplifier senses and amplifies a data signal when it is applied from a unit cell to a bit line, and then provides it to a local line which is a first data transfer line. The second sense amplifier senses and amplifies a data signal applied to a local line, and then delivers it to a global line which is a second data transfer line. The data output circuit accepts the data signal transferred to the global line and delivers the same to the data input/output pad. During the write operation, the data signal received through the input/output pad is stored in the unit cell via the global line and the local line and two sense amplifiers.
While no data is transferred to the global line and the local line, each is set to a precharge voltage. In general, one pair of local lines conveys one data signal differentially, and therefore, a total of three lines, one pair of local lines and a precharge line for carrying the precharge voltage, are disposed in an area where the local lines are provided.
The semiconductor memory device is provided with a plurality of banks, each of which has a multiplicity of unit cells, and a decoder capable of decoding the unit cells. As the degree of integration of the semiconductor memory device is improved, the number of unit cells prepared in one bank is gradually increased. Thus, the data lines for access of data stored in one bank become increasingly complicated.
The plurality of unit cells prepared in one bank is grouped by a plurality of cell mats, respectively. A data line for carrying data stored in the unit cell of each cell mat is arranged in each hall region formed between the cell mats. The data line arranged in the hall region includes one pair of local lines and the precharge line for precharge of the local lines.
Since all of these three lines are arranged between the cell mats provided in the bank, a circuit area occupied by these three data lines is quite large out of the whole circuit area of the bank.
For integration of the semiconductor memory device, it is necessary to reduce the circuit area of the bank, but there is a difficulty in doing so due to the data lines disposed between the cell mats.